The present invention relates to a BiCMOS device and a manufacturing method thereof, and more particularly, to a bipolar transistor by which a problem of lowered reliability is solved, and a manufacturing method thereof.
A BiCMOS technique, which attains high speed operation and low current consumption by incorporating a bipolar transistor and a MOS transistor into one chip in order to take advantage of benefits of each device, has been widely adopted in the semiconductor memory field. Several methods for manufacturing various types of bipolar transistors have been proposed for a BiCMOS manufacturing technique to optimize the function of the bipolar and MOS transistors. Here, typical structures include a selectively ion-implanted collector (SIC) and a base electrode surround emitter transistor (BEST). In particular, a high-concentration buried layer fabrication process and an epitaxial process are essential for manufacturing a high-performance bipolar transistor.
FIG. 1 is a cross-sectional view of a BiCMOS structure manufactured by a first conventional method, in which an epitaxial process is performed to form the bipolar and MOS transistors and a high-concentration buried layer is formed in the lower portions of the respective devices, for reducing the surface resistance of a collector and for efficient inter-device insulation. In FIG. 1, a periphery circuit region includes a bipolar transistor and a PMOS transistor, and an SRAM cell region includes an NMOS and a high-resistance polysilicon layer.
In the above constitution, N-type high-concentration buried layer 3 and P-type buried layer 5 are selectively formed in the vicinity of the surface of a semiconductor substrate 1, and an epitaxial layer (epi) is formed thereon. An N-well 7 is formed within the epitaxial layer over the N-type high-concentration buried layer 3, and a P-well 9 is formed within the epitaxial layer over the P-type buried layer 5. The bipolar transistor and the PMOS transistor are formed within N-well 7 so as to be insulated from each other, and an NMOS transistor is formed within P-well 9. The bipolar transistor comprises a collector impurity layer having N-well 7 and high-concentration collector impurity layer 11, base impurity layer 13, and emitter impurity layer 15. Here, the high-concentration collector impurity layer 11 is formed to be connected with N-type high-concentration buried layer 3. The PMOS transistor is composed of a P-type source/drain region 17 and a gate electrode 25, and the NMOS transistor is composed of an N-type source/drain regions 19 and a gate electrode 26. High-resistance polysilicon layer 29 of the SRAM cell is connected with one portion of source/drain region 19 of the NMOS transistor. Emitter impurity layer 15 and the other portion of the source/drain region 19 are connected with electrodes 35 and 43 via pad layers 23 and 31, respectively. Collector electrode 33 of the bipolar transistor is connected with high-concentration collector impurity layer 11. A base electrode 37 is connected with base impurity layer 13. Source/drain electrodes 39 of the PMOS transistor are respectively connected with source/drain regions 17. Also, reference numeral 21 denotes a field oxide layer, and reference numerals 27 and 45 denote insulation layers.
The BiCMOS manufactured by the first conventional method must undergo successive procedures of selectively forming high-concentration buried layer 3 and buried layer 5 on the surface of a semiconductor substrate, growing an epitaxial layer of 1.about.2.mu.m on the whole surface thereof, forming an N-well or P-well in the epitaxial layer, and forming a bipolar transistor and MOS transistors within the well.
When comparing the conventional CMOS manufacturing process and the aforementioned BiCMOS manufacturing process, the latter is more difficult (i.e., more complicated) than the conventional one which is performed by merely forming a MOS transistor within an N-well or P-well formed in the substrate, in that it necessitates the further steps of forming a high-concentration buried layer and an epitaxial layer. Particularly, the epitaxial layer forming process requires a high-precision technique, which is time-consuming and costly.
In order to abate the above complexity and, in doing so, save processing time and cost, there is a BiCMOS manufacturing technique which eliminates the heretofore essential processes of forming a high-concentration buried layer and epitaxial layer. Here, a bipolar transistor and a MOS transistor are formed in a well which is formed in a substrate.
FIG. 2 is a cross-sectional view of a bipolar transistor manufactured by a second conventional method for forming a BiCMOS structure, in which a well is formed in a semiconductor substrate and then a bipolar transistor is formed within the well. Unlike the first conventional method by which, after forming an epitaxial layer on a semiconductor substrate, a well is formed in the epitaxial layer and active devices are formed within the well. In FIG. 2, only the bipolar transistor of a BiCMOS is shown because this is where the most severe reduction in performance occurs when the high-concentration buried layer and epitaxial layer are not formed. (Although not shown, it is assumed that MOS transistors are formed around the bipolar transistor.)
Referring to FIG. 2, after forming N-well 52 and P-well 54 by selectively injecting impurity ions into a semiconductor substrate 50, a field oxide layer 62 is formed on the surface of the substrate by selective thermal oxidation. Subsequently, high concentration N-impurities are injected into a predetermined region, to form high-concentration collector impurity layer 56. Thereafter, high concentration P-type impurities are selectively injected to form a high concentration P-impurity layer 64 and base impurity layer 58 for an ohmic contact. Next, the impurities of a pad layer 70, on which an impurity-doped polysilicon and silicide are deposited, diffuse into the semiconductor substrate, thereby forming an emitter impurity layer 60. Then, electrodes 72, 74, 76 and 78 are formed by a conventional method.
According to the second conventional bipolar transistor manufacturing method, as the processes for forming the high-concentration buried layer and epitaxial layer are omitted, the overall manufacturing process is simplified, thereby reducing the processing time and cost. However, the following characteristic deterioration of the bipolar transistor typically becomes noticeable.
First, the influence of parasitic bipolar transistors becomes prominent, which affects the operation of a BiCMOS logic gate. As shown in FIG. 2, a PNP parasitic bipolar transistor is composed of a base impurity layer 58 of the bipolar transistor, N-well 52, and P-impurity layer 64 formed on P-well 54.
Secondly, collector resistance is increased, thereby lowering the operational speed of a device. Since the current passing through emitter impurity layer 60 and base impurity layer 58 flows unidirectionally by the voltage applied to collector electrode 72, i.e., from base impurity layer 58 to high-concentration collector impurity layer 56, the resistance of the path along which the current flows becomes relatively high.